If it is useful rpy me ... I will post CTS VLSI interview questions.

Suresh

My Experience In HCL VLSI interview

Hi everybody,
I have attened HCL VLSI(FPGA DESIGN) Interview in chennai. I got lot of experience in that interview.Just i want share the questions which they asked.
1. they mainly focused on three things DIGITAL,LANGUAGE,VERIFICATION.
IN DIGITAL:
what will you do if two systems acts in a different clock frequency?
what is the different between FIFO and RAM?
how to calculate FIFO dept in syn and asyn FIFO?
There is a block box which should give sequence 2,3,4,5. how to design external circuit?
Design clk div/2 circuit?
div/3 circuit for 50% duty cycle?
mod counter design circuit?
design a counter from clock divider logic?
what is mean setup,hold time?
how to calculate max freq?
what is metastability?
how to avoid it?what is mean by MTBF?
and,or,xnor gate design using Mux circuit?
In above realization what will u do if there is no Vcc,Gnd pin?
Design a circuit for swapping Two numbers?
IN LANGUAGE

what is the diff bt VHDL/Verilog?
write logic for clock div/3 in a single program?
write sequence detector for 110110011 value?
how to design tristate buffer using verilog?
what is diff bt
syn,asyn reset?
block,non blockin?
write program for swapping two no in verilog?
(ALL Questions in verilog only.Focus on verilog,SV,DIGITAL).

They asked about verification,system verilog. I said i dont have exp in that. After 1.30 hour interviw finished.
All the Best.
reply me if u like it , I will post my CTS VLSI interview Questions
SURESH